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revision 2.1 jan. 2004 1 a4 a3 a2 a1 a0 ce dq0 dq1 dq2 dq3 vcc gnd dq4 dq5 dq6 dq7 we a17 a16 a15 a14 a13 a5 a6 a7 oe ub lb dq15 dq14 dq13 dq12 gnd vcc dq11 dq10 dq9 dq8 nc a8 a9 a10 a11 a12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 62wv25616ec 62wv25616ei r0 201-STC62WV25616 power dissipation speed ( ns ) standby ( i ccsb1 , max ) ( i cc , max ) product family operating temperature vcc range 55ns :3.0~5.5v vcc= 3.0v vcc = 3.0v pkg type STC62WV25616dc dice STC62WV25616ec tsop2-44 STC62WV25616ac bga-4 8-0608 +0 o c to +70 o c 2.4v ~ 5.5v 55 /70 5ua 30ua 21ma 53ma STC62WV25616di dice STC62WV25616ei tsop2-44 STC62WV25616ai bga-4 8-0608 -40 o c to +85 o c 2.4v ~ 5.5v 55 /70 10ua 60ua 22ma 55ma very low power/voltage cmos sram 256k x 16 bit ? wide vcc operation voltage : 2.4~5.5v ? very low power consumption : vcc = 3.0v c-grade: 26ma (@55ns) operating current i-grade: 27ma (@55ns) operating current c-grade: 21ma (@70ns) operating current i-grade: 22ma (@70ns) operating current 0.45ua (typ.) cmos standby current vcc = 5.0v c-grade: 63ma (@55ns) operating current i-grade: 65ma (@55ns) operating current c-grade: 53ma (@70ns) operating current i-grade: 55ma (@70ns) operating current 2.0ua (typ.) cmos standby current ? high speed access time : -55 55ns -70 70ns ? automatic power down when chip is deselected ? three state outputs and ttl compatible ? fully static operation t he STC62WV25616 is a high performance, ve ry low pow er cmos static random access memory organized as 262,144 words by 16 bits and operates from a wide range of 2.4v to 5.5v supply voltage. advanced cmos technology and circuit techniques provide both high speed and low power features with a typical cmos standby current of 0.45ua at 3.0v/25 o c and maximum access time of 55ns at 3.0v/85 o c. easy memory expansion is provided by an active low chip enable (ce) ,active low output enable(oe) and three-state output drivers. the STC62WV25616 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. t he STC62WV25616 is available in dice form, jedec standard 4 4-pin tsop type ii package and 48-ball bga package. ? description ? features row decoder memory array 2048 x 2048 column i/o write driver sense amp column decoder data buffer output a9 a8 a7 data buffer input control gnd vcc oe we ce dq15 dq0 a0 a13 a14 a15 a1 a2 16 16 16 16 14 128 2048 ? block diagram 2048 22 a17 a16 a10 a12 a6 a11 a3 address input buffer a5 address input buffer . . . . ub . . . . lb ? product family ? pin configurations stc international limited . reserves the right to modi fy document contents without notice. STC62WV25616 a4 stc operating ? data retention supply v oltage as low as 1. 5v ? easy expansion with ce and oe options ? i/o configuration x8/x16 selectable by lb and ub pin vcc= 5.0v vcc = 5.0v 70ns :2.7~5.5v 70ns 70ns .com .com .com
revision 2.1 jan. 2004 2 r0 201-STC62WV25616 name function a0-a17 address input these 18 address inputs select one of the 262,144 x 16-bit words in the ram. ce chip enable input ce is active low. chip enables must be active when data read from or write to the device. if chip enable is not active, the device is deselected and is in a standby power mode. the dq pins will be in the high impedance state when the device is deselected. we write enable input the write enable input is active low and controls read and write operations. with the chip selected, when we is high and oe is low, output data will be present on the dq pins; when we is low, the data present on the dq pins will be written into the selected memory location. oe output enable input the output enable input is active low. if the output enable is active while the chip is selected and the write enable is inactive, data will be present on the dq pins and they will be enabled. the dq pins will be in the high impedance state when oe is inactive. lb and ub data byte control input lower byte and upper byte data input/output control pins. dq0 - dq15 data input/output ports these 16 bi-directional ports are used to read data from or write data into the ram. vcc power supply gnd ground ? truth table ? pin descriptions stc STC62WV25616 mode ce we oe lb ub d0~d7 d8~d15 vcc current h x x x x high z high z i ccsb , i ccsb1 not selected (power down) x x x h h high z high z i ccsb , i ccsb1 output disabled l h h x x high z high z i cc l l dout dout i cc h l high z dout i cc read l h l l h dout high z i cc ll din din i cc hl x din i cc write l l x lh din x i cc l xx h h high z high z i cc .com .com .com .com
revision 2.1 jan. 2004 3 c in input capacitance v in =0v 6 pf c dq input/output capacitance v i/o =0v 8 pf range ambient temperature vcc commercial 0 o c to +70 o c 2.4v ~ 5.5v industrial -40 o c to +85 o c 2.4v ~ 5.5v 1. typical characteristics are at t a = 25 o c. 2. these are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. fmax = 1/t rc . 4. icc sb1_max. is 5ua/30ua at vcc=3.0v/5.0v and t a =70 o c. 5. icc_ max . is 27ma(@3.0v)/65ma(@5.0v) under 55ns operation. ? absolute maximum ratings (1) ? operating range ? capacitance (1) (ta = 25 o c, f = 1.0 mhz) 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 1. this parameter is guaranteed and not 100% tested. ? dc electrical characteristics ( ta = -40 to + 85 o c ) symbol parameter rating units v term terminal voltage with respect to gnd -0.5 to vcc+0.5 v t bias temperature under bias -40 to +85 o c t stg storage temperature -60 to +150 o c p t power dissipation 1.0 w i out dc output current 20 ma stc STC62WV25616 parameter name parameter test conditions min. typ. (1) max. units vcc=3.0v 0.8 v il guaranteed input low voltage (2) -0.5 -- v vcc=3.0v 2.0 v ih guaranteed input high voltage (2) -- vcc+0.3 v i il input leakage current vcc = max, v in = 0v to vcc -- -- 1 ua i lo output leakage current vcc = max, ce = v ih , or oe = v ih , v i/o = 0v to vcc -- -- 1 ua vcc=3.0v v ol output low voltage -- -- v vcc=3.0v v oh output high voltage -- -- v vcc=3.0v 22 i cc operating power supply current ce=v il ,i dq = 0ma, f=fmax (3) -- -- ma vcc=3.0v 0.5 i ccsb standby current-ttl ce = v ih , i dq = 0ma -- -- ma vcc=3.0v 0.45 10 i ccsb1 standby current-cmos ce R R Q .com .com .com .com
revision 2.1 jan. 2004 4 stc STC62WV25616 symbol parameter test conditions min. typ. (1) max. units v dr vcc for data retention ce
vcc - 0.2v v in
vcc - 0.2v or v in 0.2v 1.5 -- -- v i ccdr data retention current ce
vcc - 0.2v v in
vcc - 0.2v or v in 0.2v -- 0.3 1.3 ua t cdr chip deselect to data retention time 0---- ns t r operation recovery time see retention waveform t rc (2) -- -- ns ? data retention characteristics ( ta = -40 to + 85 o c ) 1. vcc = 1.5v, t a = + 25 o c 2. t rc = read cycle time 3. i cc dr _ max. is 0.8ua at t a =70 o c. r0 201-STC62WV25616 ? low v cc data retention waveform ( ce controlled ) ce data retention mode vcc t cdr vcc t r v ih v ih vcc v dr 1.5v .com .com .com .com
revision 2.1 jan. 2004 5 r0 201-STC62WV25616 ? ac electrical characteristics ( ta = -40 to + 85 o c ) read cycle ? ac test conditions (test load and input/output reference) ? key to switching waveforms waveform inputs outputs must be steady may change from h to l don t care: any change permitted does not apply must be steady will be change from h to l change : state unknown center line is high impedance ?off ?state may change from l to h will be change from l to h , stc STC62WV25616 input pulse levels vcc / 0v input rise and fall times 1v/ns input and output timing reference level 0.5vcc output load c l = 30pf+1ttl c l = 100pf+1ttl jedec parameter name parameter name description (vcc = 2.7~5.5v) (vcc = 3.0~5.5v) unit t avax t rc read cycle time 70 -- -- 55 -- -- ns t avqv t aa address access time -- -- 70 -- -- 55 ns t elqv t acs chip select access time -- -- 70 -- -- 55 ns t ba t ba data byte control access time (lb,ub)----35----30 ns t glqv t oe output enable to output valid -- -- 35 -- -- 30 ns t e1lqx t clz chip select to output low z 10 -- -- 10 -- -- ns t be t be data byte control to output low z (lb,ub) 5 -- -- 5 -- -- ns t glqx t olz output enable to output in low z 5----5---- ns t ehqz t chz chip deselect to output in high z -- -- 35 -- -- 30 ns t bdo t bdo data byte control to output high z (lb,ub) -- -- 35 -- -- 30 ns t ghqz t ohz output disable to output in high z -- -- 30 -- -- 25 ns t axox t oh data hold from address change 10 -- -- 10 -- -- ns (1) note : min. typ. max. min. typ. max. 1. t ba is 35ns/30ns (@speed=70ns/55ns) with address toggle. ; t ba is 70ns/55ns (@speed=70ns/55ns) without address toggle. cycle time : 70ns cycle time : 55ns .com .com .com .com
revision 2.1 jan. 2004 6 r0 201-STC62WV25616 notes: 1. we is high in read cycle. 2. device is continuously selected when ce = v il . 3. address valid prior to or coincident with ce transition low. 4. oe = v il . 5. the parameter is guaranteed but not 100% tested. stc STC62WV25616 t oh read cycle3 (1,4) t rc t oe d out lb,ub ce oe address t clz t acs t chz (1,5) t ohz t olz t aa read cycle2 (1,3,4) t clz t chz d out lb,ub ce t ba t acs t be t bdo t bdo t ba t be (5) (5) (5) (5) ? switching waveforms (read cycle) read cycle1 (1,2,4) t rc t oh t aa d out address t oh .com .com .com .com
revision 2.1 jan. 2004 7 r0 201-STC62WV25616 ? switching waveforms (write cycle) stc STC62WV25616 t wr write cycle1 (1) t wc (3) t cw (10) t bw (2) t wp t aw t ohz (4,11) t as (3) t dh t dw d in d out we lb,ub ce oe address (5) ? ac electrical characteristics ( ta = -40 to + 85 o c ) jedec parameter name parameter name description (vcc = 2.7~5.5v) (vcc = 3.0~5.5v) unit t avax t wc write cycle time 70 -- -- 55 -- -- ns t e1lwh t cw chip select to end of write 70 -- -- 55 -- -- ns t avwl t as address setup time 0 -- -- 0 -- -- ns t avwh t aw address valid to end of write 70 -- -- 55 -- -- ns t wlwh t wp write pulse width 35 -- -- 30 -- -- ns t whax t wr write recovery time (ce,we) 0 -- -- 0 -- -- ns t bw t bw date byte control to end of write (lb,ub) 30 -- -- 25 -- -- ns t wlqz t whz write to output in high z -- -- 30 -- -- 25 ns t dvwh t dw data to write time overlap 30 -- -- 25 -- -- ns t whdx t dh data hold from write time 0 -- -- 0 -- -- ns t ghqz t ohz output disable to output in high z -- -- 30 -- -- 25 ns t whox t ow end of write to output active 5 -- -- 5 -- -- ns write cycle 1. t bw is 30ns/25ns (@speed=70ns/55ns) with address toggle. ; t bw is 70ns/55ns (@speed=70ns/55ns) without address toggle. (1) note : min. typ. max. min. typ. max. cycle time : 70ns cycle time : 55ns .com .com .com .com
revision 2.1 jan. 2004 8 r0 201-STC62WV25616 write cycle2 (1,6) stc STC62WV25616 t wc t cw (10) (2) t wp t aw t whz (4,11) t as t wr (3) t dh t dw d in d out we ce address (5) t ow (7) (8) (8,9) t bw lb,ub notes: 1. we must be high during address transitions. 2. the internal write time of the memory is defined by the overlap of ce and we low. all signals must be active to initiate a write and any one signal can terminate a write by going inactive. the data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. t wr is measured from the earlier of ce or we going high at the end of write cycle. 4. during this period, dq pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. if the ce low transition occurs simultaneously with the we low transitions or after the we transition, output remain in a high impedance state. 6. oe is continuously low (oe = v il ). 7. d out is the same phase of write data of this write cycle. 8. d out is the read data of next address. 9. if ce is low during this period, dq pins are in the output state. then the data input signals of opposite phase to the outputs must not be applied to them. 10. t cw is measured from the later of ce going low to the end of write. 11. the parameter is guaranteed but not 100% tested. .com .com .com .com
revision 2.1 jan. 2004 9 r0 201-STC62WV25616 ? ordering information stc STC62WV25616 ? package dimensions tsop2-44 note: bsi (brilliance semiconductor inc.) assumes no responsibility for the application or use of any product or circuit described he rein. bsi does not authorize its products for use as critical components in any application in which the failure of the bsi product may be expected to result in signif icant injury or death, including life-support systems and critical medical instruments. STC62WV25616 x x y y grade c: +0 o c ~ +70 o c i: -40 o c ~ +85 o c speed 55: 55ns 70: 70ns pkg material -: normal g: green p: pb free package e: tsop2-44 a: bga-48-0608 d: dice .com .com .com .com
revision 2.1 jan. 2004 10 STC62WV25616 stc r0 201-STC62WV25616 ? package dimensions (continued) 48 mini-bga (6 x 8mm) e0.1 3: symbol "n" is the number of solder balls. 1: controlling dimensions are in millimeters. 2: pin#1 dot marking by laser or pad print. n e d notes: 48 8.0 6.0 e1 d1 3.75 5.25 side view d0.1 d1 1.4 max. e e1 0.25 d 0.05 solder ball 0.35 d 0.05 view a d .com .com .com

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